- #DSP BUILDER AND KALMAN FILTER FULL#
- #DSP BUILDER AND KALMAN FILTER PRO#
- #DSP BUILDER AND KALMAN FILTER SOFTWARE#
- #DSP BUILDER AND KALMAN FILTER CODE#
Converted existing Xilinx Confidential schematics to VHDL and created test bench for code coverage, toggle coverage, path coverage, expression coverage, branch coverage, and profiler coverage using Active-HDL. Contract was completed and DOD sequestration was in effect. Completed both LP and HP (Notch Filter) distributed component designs utilizing LINC2 and SONNET. Designed Diplexer for UAT ADS-B Transceiver (978 MHz) RF multiplexing with ATCRBS Transponder (1030 MHz and 1090 MHz). All work was done with Mentor Graphics ModelSim SE, Synopsys Synplify Pro, and Actel Leonardo Spectrum. #DSP BUILDER AND KALMAN FILTER FULL#
Enhanced existing Confidential design and VHDL test bench for GE38 jet turbine rate sensor as part of Full Authority Digital Electronic Control (FADEC). Wrote test- benches for DO-254 testing requirements. Developed Confidential design for ARINC429 System on a Chip which included a single transmitter and receiver. Designed DSP algorithms with MATLAB Simulink and utilized HDL Coder for auto-generating RTL code, and executed Embedded Coder (Real-Time Workshop) for creating C code of DSP algorithms. Utilized Xilinx SysGen DSP builder to create Core Generated VHDL code. Utilized Enovia Synchronicity DesignSync configuration tool for all designs. Created complex state machines with Active-HDL (FSM Editor) which used multiple VHDL processes. Simulated VHDL designs with ModelSim and Active-HDL. Synthesized VHDL designs with Synplify Pro, placed and routed with Xilinx Vivado which targeted the Xilinx Kintex Confidential device. Implemented control and status registers, SPI interface, and RF discretes for Intelligent Test Adapters. #DSP BUILDER AND KALMAN FILTER SOFTWARE#
Design high speed VHDL code for Software Definable Radios. Design was modified so as to work with Lattice Diamond PAR tools, utilized “Synplify Pro” for synthesis and ModelSim for “timed” simulations using post PAR Simulation Delay Files (SDF). Remote work done on transferring a 32 MHz design from a “Cool Runner” Xilinx CPLD to a Lattice CPLD. Hardware designs were completed and contract was terminated. Mentored CO-OP’s in every facet of the design process. Performed “timed” simulations with SDF files utilizing ModelSim. #DSP BUILDER AND KALMAN FILTER PRO#
Utilized Actel Libero Designer for PAR and Synplify Pro for synthesis. Components designed included a “timestamp” for MIL1553 bus messages, PWM excitation outputs for Linear Voltage Differential Transducers (LVDT’s), “STATE CONTROLLER” sequencer which mitigated SEU’s, and an ADC controller followed by demodulation to obtain positional data from the LVDT’s. Created MATLAB/SIMULINK model and used “COSIM” capability to test Confidential design. Design operated at 32MHz utilizing Actel RTAX Confidential with triple redundancy. 
Developed VHDL code for a hydraulic control actuator system. Contract was for a short duration and not perm. 
Created Verilog Bus Functional Models for test bench simulation runs of a Software Definable Radio (SDR) design. Developed several Finite State Machines with SEU mitigation as part of the SPI interface. Xilinx Vivado, ModelSim, and ALDEC Active-HDL ALINT were tools used to complete the design. Used AXI4 Memory Mapped, AXI4 Streaming, and AXI4 Lite network topology for both interfaces. Responsible for VHDL designs utilizing the Xilinx Artix Confidential, which interfaced to a TI Codec through SPI and I2S interfaces. Linux work environment used to run modified scripts for Clocks/CDC to check for Clock Domain Boundary Crossing issues as part of Questa Verify. Utilized Synplify Pro, Questa Sim, Questa Verify, Quartus II, and Matlab Simulink Co-simulation to analyze and trouble-shoot latest designs on Confidential ArriaV, CycloneV, and Stratix Confidential ’S. 
PROGRAMMING LANGUAGES: C, PASCAL, FORTH, PETRI-NET, FORTRAN, Liberty Basic (Visual Basic)Ĭonfidential, Cedar Rapids, IA Electronic Controls Engineer Matlab, Simulink, Rtw, Poses, Neural Network, Hybrid, Petri-Net, Vme, Siemens, Plc, Simatic, S7, Wincc Hmi, Kalman Filter, Dsp, Aldec, Active-Hdl, Modelsim, Vhdl,Verilog, Orcad, Pspice, Pads, Blazerouter, Xilinx, Vivado, Actel, Libero, Confidential, Psos, Vxworks,Fuzzy Logic, Simulation,Dvm, Oscilloscope, Logic Analyzer, Spectrum Analyzer, Vector Analyzer, Hp Advisor, Protocol Analyzer, Ethernet, Tcp/Ip, Udp/Ip, Perl, Xcel, Cvs, Svn, Unix, Linux, C, Pascal, Forth,Fortran, Texas Instruments, Analog Devices, Cypress, Serial, Hilt, And PassportĪREAS OF SKILLS, ABILITIES, AND EXPERTISE INCLUDE: DSP Electrical/Electronic Controls Engineer seeking employmentfor distributed control systems, MATLAB Simulink modeling, Kalman Filter design, ladder logic PLC programming, VHDL Confidential design,or embedded firmware design for real - time operating system.
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